From 9b4242c57c9c24c061320ffd1b94b0a6132f0737 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Fri, 11 Sep 2026 22:12:55 +0530 Subject: [PATCH 1/2] FROMLIST: arm64: dts: qcom: glymur: Add UFS nodes Add UFS PHY and UFS host controller nodes for Glymur SoC. Link: https://lore.kernel.org/all/20260911-glymur_ufs_qcb_enablement-v1-3-b9fc5e2ee99a@oss.qualcomm.com/ Signed-off-by: Pradeep P V K --- arch/arm64/boot/dts/qcom/glymur.dtsi | 114 ++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 3705f07f1e735..cc7f466cd9c98 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -830,9 +830,9 @@ <0>, /* QUSB4 1 PHY RX 1 */ <0>, /* QUSB4 2 PHY RX 0 */ <0>, /* QUSB4 2 PHY RX 1 */ - <0>, /* UFS PHY RX Symbol 0 */ - <0>, /* UFS PHY RX Symbol 1 */ - <0>, /* UFS PHY TX Symbol 0 */ + <&ufs_mem_phy 0>, /* UFS PHY RX Symbol 0 */ + <&ufs_mem_phy 1>, /* UFS PHY RX Symbol 1 */ + <&ufs_mem_phy 2>, /* UFS PHY TX Symbol 0 */ <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, @@ -4354,6 +4354,114 @@ reg = <0x0 0x010c3000 0x0 0x1000>; }; + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,glymur-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + /* UFS and PCIE4 shares the same clkref on glymur */ + <&tcsr TCSR_PCIE_4_CLKREF_EN>; + + clock-names = "ref", + "ref_aux", + "qref"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufshc@1d84000 { + compatible = "qcom,glymur-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x01da0000 0x0 0x15000>; + + reg-names = "std", + "mcq"; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 = <&ufs_opp_table>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre2_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x460 0>; + dma-coherent; + + msi-parent = <&gic_its 0x460>; + lanes-per-direction = <2>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <100000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-403000000 { + opp-hz = /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <403000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; From c88b0eb1a3370f3d323771006979b28ba17408f3 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Fri, 11 Sep 2026 22:12:56 +0530 Subject: [PATCH 2/2] FROMLIST: arm64: dts: qcom: glymur-qcb: Enable UFS Enable UFS for glymur-qcb board. Link: https://lore.kernel.org/all/20260911-glymur_ufs_qcb_enablement-v1-4-b9fc5e2ee99a@oss.qualcomm.com/ Signed-off-by: Pradeep P V K --- arch/arm64/boot/dts/qcom/glymur-qcb.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-qcb.dts b/arch/arm64/boot/dts/qcom/glymur-qcb.dts index 17d8ff3aed23b..b6e384024dfff 100644 --- a/arch/arm64/boot/dts/qcom/glymur-qcb.dts +++ b/arch/arm64/boot/dts/qcom/glymur-qcb.dts @@ -697,3 +697,21 @@ vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>; }; }; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1c_e1_0p82>; + vdda-pll-supply = <&vreg_l4f_e1_1p08>; + + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 250 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_e0_2p4>; + vcc-max-microamp = <1200000>; + vccq-supply = <&vreg_l12b_e0_1p14>; + vccq-max-microamp = <1200000>; + + status = "okay"; +};