diff --git a/crates/core_arch/src/amdgpu/mod.rs b/crates/core_arch/src/amdgpu/mod.rs
index 856fb840aa..00182f154c 100644
--- a/crates/core_arch/src/amdgpu/mod.rs
+++ b/crates/core_arch/src/amdgpu/mod.rs
@@ -351,7 +351,7 @@ pub unsafe fn sched_barrier<const MASK: u32>() {
 /// Combining multiple `sched_group_barrier` intrinsics enables an ordering of specific instruction types during instruction scheduling.
 /// For example, the following enforces a sequence of 1 VMEM read, followed by 1 VALU instruction, followed by 5 MFMA instructions.
 ///
-/// ```ignore
+/// ```ignore (only available on AMD)
 /// // 1 VMEM read
 /// sched_group_barrier::<32, 1, 0>();
 /// // 1 VALU
diff --git a/crates/core_arch/src/nvptx/mod.rs b/crates/core_arch/src/nvptx/mod.rs
index df682b6c6e..53d53d1e1e 100644
--- a/crates/core_arch/src/nvptx/mod.rs
+++ b/crates/core_arch/src/nvptx/mod.rs
@@ -157,10 +157,13 @@ unsafe extern "C" {
     /// * `format`: A pointer to the format specifier input (uses common `printf` format).
     /// * `valist`: A pointer to the valist input.
     ///
-    /// ```ignore
+    /// ```ignore (available only for nvptx)
+    /// # use std::mem::transmute;
     /// #[repr(C)]
     /// struct PrintArgs(f32, f32, f32, i32);
     ///
+    /// let a = 0.1f32;
+    /// let b = 0.2f32;
     /// vprintf(
     ///     "int(%f + %f) = int(%f) = %d\n".as_ptr(),
     ///     transmute(&PrintArgs(a, b, a + b, (a + b) as i32)),
diff --git a/rust-version b/rust-version
index 7b240b9797..61a4b2d8c0 100644
--- a/rust-version
+++ b/rust-version
@@ -1 +1 @@
-fcbe7917ba18120d9eda136f1c7c5a60c78e554e
+1e5ee356374211706221b71b6106d297a646ee57