perf(gc): align barrier gate load ordering - #7935
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📝 WalkthroughWalkthroughThe change aligns incremental-barrier active-counter reads across runtime and generated code. Runtime readers use relaxed ordering, generated LLVM loads use monotonic ordering, and tests verify the atomic load contract across barrier gate families. ChangesIncremental barrier ordering
Estimated code review effort: 3 (Moderate) | ~20 minutes Possibly related PRs
🚥 Pre-merge checks | ✅ 5✅ Passed checks (5 passed)
✨ Finishing Touches📝 Generate docstrings
🧪 Generate unit tests (beta)
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Summary
PERRY_INCREMENTAL_MARK_BARRIER_ACTIVE_COUNTgate as an LLVMmonotonicload, matching Rust'sRelaxedreadersWhy
Relaxedis sufficientThe counter does not publish the
ValidPointerSetor any other memory. It only decides whether the current thread should pay for a TLS read and barrier call.Arming increments the counter before installing the current thread's TLS pointer. Disarming clears that pointer before decrementing the counter. A later relaxed load on an armed thread therefore cannot observe a counter value preceding its own increment, and the count cannot return to zero until that thread removes its contribution. A thread with a null TLS pointer may conservatively observe either value: skipping the call on zero is equivalent to the call reading null and returning. There is no cross-thread data for an acquire load to publish.
Validation
seq_cstcargo test -p perry-codegen: passed in fullcargo test -p perry-runtime: 2,194 passed, 0 failed, 4 ignoredmain: 5 passed, 0 failedcargo fmt --all -- --checkbash scripts/check_file_size.shPerformance
Built separate compiler/runtime pairs for base and fix and compiled
gc-handoff/apps/interp.tswith each. Both arms printed1708840, exited 0, and produced the same 13,709,320-byte executable size.Machine code changed as intended: whole-binary
ldarcount 779 -> 44 andldrcount 229,093 -> 229,828 (735 matching replacements).On the quiet M1 mini (load 1.60-1.99, no foreign benchmark/build processes), two order-reversed 31-pair sweeps were neutral:
Instructions were unchanged, as expected for one instruction replacing one instruction; best cycles moved -0.14%. This resolves the reader/documentation disagreement without a measurable regression, but the profiled
ldarwas not a standalone speedup.Closes #7918
Summary by CodeRabbit
Performance
Bug Fixes
Tests