[backport] riscv: Implement smp_cond_load8/16() with Zawrs - #371
Conversation
|
开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/32363783546 参数解析结果
测试完成 详细结果:
Kunit Test Result[11:30:53] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)
result: Lava check done!
|
|
@uestc-gr 上周 rvck-6.6 升级了,请 rebase 一下再 review,谢谢 |
mainline inclusion from Linux 6.14-rc7 commit d9708b1 category: feature bugzilla: RVCK-Project#367 -------------------------------- RISC-V code uses the queued spinlock implementation, which calls the macros smp_cond_load_acquire for one byte. So, complement the implementation of byte and halfword versions. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Cc: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Link: https://lore.kernel.org/r/20241217013910.1039923-1-guoren@kernel.org Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Signed-off-by: Gao Rui <gao.rui@zte.com.cn>
|
开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/32696551465 参数解析结果
测试完成 详细结果:
Kunit Test Result[06:20:15] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)
result: Lava check fail!
测试完成 详细结果:
Kunit Test Result[06:20:15] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)
result: Lava check fail!
|
|
开始测试 log: https://github.com/RVCK-Project/rvck/actions/runs/32696551465 参数解析结果
测试完成 详细结果:
Kunit Test Result[09:08:59] Testing complete. Ran 482 tests: passed: 465, skipped: 17
Kernel Build Result
Check Patch Result
LAVA Check (qemu)
result: Lava check done!
|
unicornx
left a comment
There was a problem hiding this comment.
LGTM
Reviewed-by: Chen Wang wangchen20@iscas.ac.cn
Tested-by: Chen Wang wangchen20@iscas.ac.cn # QEMU
|
test.tar.gz Also:
|
|
LGTM Reviewed-by: Fangyu Yu fangyu.yu@linux.alibaba.com |
|
已经合并至rvck-6.6. |
fixed: #367
补丁 riscv: Implement smp_cond_load8/16() with Zawrs 在 arch/riscv/include/asm/cmpxchg.h 中新增了对 byte (8-bit) 和 halfword (16-bit) 的 smp_cond_load 实现,利用 Zawrs 指令扩展 (WRS.NTO) 来优化自旋锁等待。
之前 RISC-V 内核只支持 word (32/64 位) 的 smp_cond_load,该补丁补齐了 8/16 位场景。
测试方法
smp_cond_load_test.c
测试结果
~ # insmod /home/smp_cond_load_test.ko
[ 42.385827] smp_cond_load_test: loading out-of-tree module taints kernel.
[ 42.478998] cmpwait_test: module init
[ 42.487520] writer: sleeping 2s before update...
[ 42.490939] reader: waiting for test_byte=0x12...
[ 44.519323] writer: updated test_byte=0x12
[ 44.519475] reader: got test_byte match!
[ 44.520820] reader: waiting for test_half=0x1234...
[ 46.534158] writer: updated test_half=0x1234
[ 46.534316] reader: got test_half match!