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Signed-off-by: Devendra Kumar <devendra.kumar@amd.com>
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Fix for issue 226 (#226)
Issue
PF2 BAR0 maps the user-region s_axi_control aperture (0x20200000000). With
CPM_PCIE1_MSI_X_OPTIONS=MSI-X_Internal and no PF2 MSI-X settings, CPM5
defaults place the PF2 MSI-X table at BAR0 0x40 (8 vectors, PBA at 0x50).
The CPM serves those TLPs internally, so host writes to kernel registers
0x40-0xBF never reach the kernel, while reads return the written value.
Fix
Relocate the PF2 MSI-X table/PBA to the unused PF2 BAR2 (0x1FFE000/0x1FFF000,
1 vector) in both the compute and service shells.
Files updated
Tested
Git dev branch commit 7a52870
Validated these changes on V80 board, and the issue is resolved
i.e. writes to args in range 0x40-0xBF complete successfully