pgw#1014: task rig:gauntlet — every mint shape in one command, plus GPU-REAL cycles on this box

[PaulFidika]

Every mint shape the fleet runs, in one command, with a table — and the first GPU-real cycles this box has ever done.

task rig:gauntlet

Four variants, each a full production cycle: real child spawn, torch.export + AOTInductor, seal, publish over the real wire, second-process discover + arm + parity. On a model that compiles in under a minute.

Variants declare the outcome they expect, because some exist to demonstrate a refusal. So the gauntlet reports agreement, not pass/fail — and a flip in either direction is news: an expected-red going green means someone fixed something and did not say so. Exit 0 = every variant matched.

variant	covers
micro	plain lane, 3 entries, container input + trailing plain input
micro-lora	lora_bucket=64, 5 entries (adapter fork), the lifted-arm gates (pgw#1001)
micro-4d	pgw#998's shape — a 4-D latent with BOTH spatial axes dynamic, so every matmul's M extent is NONLINEAR in the traced symbols. This is z-image's declaration
micro-lora-plain-parent	expected RED — a bucket-bearing cell offered to a plain-lane parent, refused at discovery with lane_mismatch before any arm runs

micro-4d being green is a result, not a formality: it re-proves pgw#998's fix on every run instead of trusting a changelog, on the exact shape z-image declares.

micro-lora-plain-parent is the standing form of pgw#999's design question, and the reason attempt 27 must dispatch the adopting pod with the cell's own bucket — that path produces no adopt event at all, which reads exactly like "the cell was never delivered".

GPU-real cycles — task rig:gpu, scripts/rig_gpu_env.sh

An isolated second interpreter with torch 2.13.0+cu126. The approved index was cu128 and it is wrong: cu128 has no torch 2.13.0, only 2.11.0, and torch is an axis verify_declared checks strictly — a cu128 cell would be further from the fleet, not closer. cu126 carries 2.13.0 and its CUDA runs on this box's 12.8 driver. The repo's .venv and the cu130 pin are untouched; the GPU interpreter is selected explicitly and is never a default.

This retires the synthetic-sm caveat. Cells now carry a measured sm_89 — the fleet's own compute capability — and the rig reports covers=plumbing + device (VRAM cap, placement, measured lane).

Carve-out, re-measured on the card before any GPU cycle was counted

card	RTX 4070 Laptop, sm_89, 7.63 GiB
budget	mint 3.00 + adopt 1.00 = 4.00 GiB (half the card)
cap actually delivered	MintRequest.vram_cap_bytes = 3.00 GiB
CardCensus	basis=sampled, 7.63 total / 7.46 free — pgw#992's pool bound, live
measured peak	0.011 GiB — 0.4% of the mint cap
GEN_WORKER_HOST_MOVE_GUARD	untouched
load gate	enforced — refused twice, at 34.5 and 72.8

Two bugs found, one of them in the instrument itself

GPU adopt, unreachable on CPU. A code-only cell binds constants from RESIDENT weights, so a CPU-resident parent adopting a CUDA cell fails inside AOTI itself (update_constant_buffer_func_ ... API call failed). The rig's adopt child is now device-aware.

The gauntlet reported a CPU row as a GPU result. The box hit load 25.6, the rig refused before any leg and exited without writing its json, and run_one read the stale json the CPU run had left at the same path — printing a CPU timing and peak under card=RTX 4070 sm_89. Caught because the row was byte-identical to the CPU run and the table's own synthetic-sm warning fired when it should not have. A green-looking number describing a run that never happened is the defect class this program keeps paying for, and it was in the instrument built to detect it. Fixed three ways: the per-variant json is deleted before each run; a REFUSED exit is its own NOT-RUN state rather than a red (a refusal is a claim about the box, a red is a claim about the mint path); and the table prints n/a.

Not built, with its exact blocker

The w8a8 leg. The lane is reachable now (w8a8_gemm_mode() answers pertensor), but swap_w8a8_linears needs a W8a8Artifact, and quantize_tree_w8a8 needs a diffusers tree (model_index.json + a vocabulary-named denoiser dir) while the micro family writes a flat single-file checkpoint. Eligibility also requires both dims 16-aligned, which in_channels=4 breaks on proj_in/proj_out. Neither is hard; both are real work, and faking either would make the leg test something other than what it claims.

Caveat that rides every GPU number from this box

The cuda identity axis is 12.6, not the fleet's 13.0. torch and sm match exactly; cuda does not — so cells minted here stay local-only. And the parity gate is cosine-based: a uniform ~1% error reads healthy, so it is a directional-degradation instrument, not a max-abs bound.