Register native pinned host memory with CUDA for GPU DMA - #8283
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mlock alone is page-locked for AIO but not device-pinned; cudaHostRegister after alloc restores torch-class H2D/D2H bandwidth. Signed-off-by: Olatunji Ruwase <tunji.ruwase@snowflake.com> Co-authored-by: Cursor <cursoragent@cursor.com>
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cudaHostUnregister must succeed before returning the allocation, or the driver can keep a registration on recycled host pages. Signed-off-by: Olatunji Ruwase <tunji.ruwase@snowflake.com> Co-authored-by: Cursor <cursoragent@cursor.com>
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Hi @sfc-gh-truwase I'm generally okay with this PR. The only thing I want to add is XPU implementation of |
@delock, good call. Please let me know when this is done. |
Summary
posix_memalign+mlock) is device-independent and sufficient for DeepNVMe, but the GPU DMA engine does not treatmlockpages as pinned. After allocation, optionally callcudaHostRegister(andcudaHostUnregisterbefore free) via accelerator hooks socopy_(..., non_blocking=True)can DMA.DS_PIN_MEMORY_REGISTER_DEVICE(1/true/yes/on;0keeps mlock-only). Registration failure logs once and continues with mlock. CPU accelerators no-op.benchmarks/pin_memory/h2d_d2h_bench.py(torch vs native-unregistered vs native-registered).H200 H2D/D2H (1 GPU)
Host
tunji-h200-n1g2-ds-pin-0, NVIDIA H200,--sizes-mib 4 64 256 --warmup 10 --iters 50, autorunjob-20260820T155549Z.torch.is_pinnedRegistered native matches torch bandwidth (~53–55 GB/s).
mlockwithoutcudaHostRegisterstays in the ~10–17 GB/s pageable range and reportstorch.is_pinned=False.Test plan
pre-commit run --fileson touched pathspytest tests/unit/v1/pin_memory/test_pin_memory.py16 passed (register on/off, CPU no-op, CUDA cudart mock, register failure keeps mlock, GC unregister, invalid env)job-20260820T155549Z: pin_memory + accelerator tests 25 passed, H2D/D2H bench exit 0Made with Cursor