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LATX, opt: Add RIP-relative and complex address caches - #466

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y347812075:perf-wi-2239
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LATX, opt: Add RIP-relative and complex address caches#466
y347812075 wants to merge 2 commits into
lat-opensource:masterfrom
y347812075:perf-wi-2239

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Summary

  • add a staged x86-64 RIP-relative immediate-address cache with safety checks,
    statistics, AOT compatibility metadata, and an explicit rollback switch
  • add base+displacement, index+displacement, and combined complex-address cache
    modes, including implicit-register invalidation and precache state tracking
  • enable all three complex-address modes by default for x86-64; keep i386,
    RIP-relative caching, and precache disabled by default
  • cover JIT/AOT, helper, signal, fork/exec, SMC, and address-state regressions

WorkItems: WI-2238, WI-2239

Configuration and rollback

  • LATX_IMM_COMPLEX=0 disables all complex-address modes.
  • LATX_IMM_REG=0000 disables the immediate-register cache master switch.
  • LATX_IMM_RIP=0 keeps the RIP-relative cache disabled.
  • LATX_IMM_PRECACHE=0 keeps precache disabled.

Validation

  • ninja -C build64 latx-x86_64
  • ninja -C build32 latx-i386
  • tests/integration/test-rip-imm-cache.sh build64/latx-x86_64 tests/integration/rip-imm-cache.S
  • tests/integration/test-complex-imm-cache.sh build64/latx-x86_64 tests/integration/complex-imm-cache.S
  • ninja -C build64-tests
  • meson test -C build64-tests --suite lat-pr-fast --print-errorlogs (24/24 passed)
  • git diff-tree --check for both commits
  • scripts/checkpatch.pl --no-tree --strict (0 errors; one generic
    MAINTAINERS warning for newly added test files)

An initial single-run SPEC CPU2000 ref screening with the complex cache fully
enabled produced a 0.43% geometric-mean runtime improvement across 176.gcc,
164.gzip, 186.crafty, and 254.gap. This is screening data rather than a stable
performance claim.

RIP-relative x86_64 memory operands repeatedly materialize nearby absolute addresses even when the same value can be retained within a translation block.

Add a separately controlled CODE64 RIP-relative immediate cache with address-size and segment safety checks, cache statistics, and explicit rollback controls. Record the mode in AOT compatibility metadata so mismatched cached code is rejected. Keep RIP-relative caching disabled by default.

Add integration coverage for JIT/AOT translation, option precedence, invalidation, signals, fork, SMC, and immediate-register pressure.

Signed-off-by: yuerengan <y347812075@163.com>
The complex-address immediate cache was disabled as a single all-or-nothing option and lacked the safety and observability needed for deployment.

Add independent base+disp, index*scale+disp, and combined mode bits with strict CODE64, address-size, and segment checks. Track complete register writes, preserve AOT cache compatibility, and report per-mode cache statistics. Enable all three modes by default for x86_64 while retaining environment and command-line rollback controls; keep i386, RIP-relative caching, and precache disabled.

Add integration coverage for default enablement, explicit disablement, addressing modes, register invalidation, helpers, signals, fork, SMC, JIT/AOT, and itemp pressure.

Tests:
- ninja -C build64 latx-x86_64
- ninja -C build32 latx-i386
- tests/integration/test-complex-imm-cache.sh build64/latx-x86_64 tests/integration/complex-imm-cache.S
- ninja -C build64-tests
- meson test -C build64-tests --suite lat-pr-fast --print-errorlogs
- SPEC CPU2000 ref: 176.gcc, 164.gzip, 186.crafty, 254.gap (mask 0 and mask 7)

Signed-off-by: yuerengan <y347812075@163.com>
@xiezyang xiezyang mentioned this pull request Sep 5, 2026
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