[transform] Target-aware register parallel dim tiling strategy - #273
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Adds register-level parallel strategy that derives tile sizes based on operations and TargetInfo. Includes shared target-capability analysis and tile-assignment helpers. Register-level strategy which directly mimics existing first-level register tiling which focuses on parallel dimension to ensure data can fit in available registers. The strategy folds in the two existing variants: general f32 and AMX bf16, and provides a generic target-aware SIMD size fallback. Assisted-by: Claude
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No new optimizations for now. The overall idea for now is to continue with further tiling steps until different matmul descriptors can be collapsed into one. |
rengolin
approved these changes
Sep 3, 2026
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Adds register-level parallel strategy that derives tile sizes based on operations and target.
Includes shared target-capability analysis and tile-assignment helpers.
Register-level strategy which directly mimics existing first-level register tiling which focuses on parallel dimension to ensure data can fit in available registers.
The strategy folds in the two existing variants: general f32 and AMX bf16, and provides a generic target-aware SIMD size fallback.
Assisted-by: Claude