Add q6b support - #603
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CodeChenL wants to merge 13 commits into
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Add q6b support#603CodeChenL wants to merge 13 commits into
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CodeChenL
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Sep 10, 2026
CodeChenL
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- 修复休眠唤醒失败
- 一些vpu特性支持的上游补丁
- 修复驱动低位宽屏幕是时钟被/2，并回退8hd不必要的修改
- 添加q6b支持
- 显性建模cm-q64的一些电源，以保持外设的稳定性
During resume, qcom_pcie_icc_opp_update() may access DBI registers before the OPP votes are restored, which can trigger NoC errors. Set the PCIe controller to the maximum OPP first in resume_noirq(), then proceed with link/DBI accesses. The OPP is later updated again based on the actual link bandwidth requirements. Also introduce a small helper to reuse the max-OPP setup path shared with probe. Fixes: 5b6272e ("PCI: qcom: Add OPP support to scale performance") Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
When validating a capture format, check_format() compares the requested pixel format against inst->fw_caps[BIT_DEPTH]. However, the bit depth capability is not available at this stage and it contains the default value of BIT_DEPTH_8. The actual bit depth is updated later after the firmware reports stream capabilities through read_input_subcr_params(). Because of this, a valid client request of QC10C format request is rejected during the initial format negotiation. The driver then falls back to the default capture format (NV12) and stores it as capture format. Later, when the firmware reports that the stream is 10-bit, the driver sees NV12 as the selected capture format and switches to the default 10-bit format (P010). As a result, the original QC10C format requested by userspace is lost and QC10C decoding cannot work correctly. The bit depth information is not reliable during the initial format setup, so it should not be used to validate capture formats. Remove the bit-depth checks from check_format() and only verify that the requested pixel format is supported. This allows the format requested by userspace is handled correctly. Fixes: 20c3ef4 ("media: qcom: iris: vdec: update find_format to handle 8bit and 10bit formats") Cc: stable@vger.kernel.org Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
The iris encoder driver was not sending HFI_PROP_TIME_DELTA_BASED_RATE_CONTROL to the firmware during encoder initialization. Without this property, the firmware defaults to time-delta-based rate control (enabled), which calculates the output bitrate from actual frame timing rather than following the configured bitrate target. This caused variable bitrate (VBR) encoding to produce ~5x configured bitrate. For example, with video_bitrate=896000 (896 Kbps), the output is ~4.4 Mbps instead of the expected ~896 Kbps. Time-delta-based rate control is designed for variable frame rate (VFR) scenarios where the encoder adapts to actual frame timing. However, when an application explicitly configures a bitrate target, the firmware must follow that target regardless of frame timing. Fix this by adding the TIME_DELTA_BASED_RC capability with a default value of 0 (disabled) and sending HFI_PROP_TIME_DELTA_BASED_RATE_CONTROL = 0 to the firmware during stream-on, allowing the firmware to use the configured bitrate as the target. Signed-off-by: Gourav Kumar <gouravk@qti.qualcomm.com> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
In iris_vpu_power_off_hw(), iris_disable_power_domains() was called before the associated clocks (IRIS_BSE_HW_CLK, IRIS_HW_AHB_CLK, IRIS_HW_CLK) were disabled and unprepared. This reverses the correct power-down sequence: with the power domain already removed, the subsequent clk_disable_unprepare() calls end up operating on clock-controller hardware that is no longer powered, which can hang or behave unpredictably. Reorder the calls so iris_disable_power_domains() runs after all three clocks are disabled, ensuring clocks are always turned off while their power domain is still active, and mirroring the reverse of the power-on sequence. Fixes: bb8a95a ("media: iris: implement power management") Cc: stable@vger.kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
iris_enum_frameintervals() advertised frame intervals using V4L2_FRMIVAL_TYPE_STEPWISE with step=1/MAXIMUM_FPS where MAXIMUM_FPS is 480. This caused client to enumerate only framerates of the form MAXIMUM_FPS/n (where n is a positive integer), restricting support to exact divisors of MAXIMUM_FPS (e.g., 480, 240, 160, 120, 96, 80, 60, 30, 24, 1). Framerates that are not exact divisors of MAXIMUM_FPS, such as 29 fps, 25 fps, were excluded from the enumerated list. There is no hardware restriction to framerates that are exact divisors of MAXIMUM_FPS. This caused GStreamer caps negotiation to fail with an "internal data stream error" when encoding content at such framerates. Fix this by using V4L2_FRMIVAL_TYPE_CONTINUOUS. With CONTINUOUS type, GStreamer creates a continuous framerate range [1, max_fps], allowing any integer framerate within the range to pass caps negotiation. The step field is set to 1/1 as required by the V4L2 specification for continuous frame intervals. Fixes: a688243 ("media: iris: Add support for ENUM_FRAMESIZES/FRAMEINTERVALS for encoder") Cc: stable@vger.kernel.org Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
Commit 93c97bc ("drm/msm: dsi: fix PLL init in bonded mode") fixed one of the issues with the DSI bonded mode, but broke non-bonded usecase for DSI as reported by Mohit Dsor. Clock divider is being programmed incorrectly, resultin in the wrong display mode being selected. Revert the offending commit, letting Neil to work on a better fix. Fixes: 93c97bc ("drm/msm: dsi: fix PLL init in bonded mode") Reported-by: Mohit Dsor <mohit.dsor@oss.qualcomm.com> Closes: https://lore.kernel.org/r/ae07cef84AmXK43H@hu-mdsor-hyd.qualcomm.com Cc: Neil Armstrong <neil.armstrong@linaro.org> Cc: Thorsten Leemhuis <regressions@leemhuis.info> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/739459/ Link: https://lore.kernel.org/r/20260712-msm-revert-dsi-pll-fix-v1-1-40122689ea25@oss.qualcomm.com
Document the machine compatibles used by the Radxa CM-Q64 compute module and Dragon Q6B board, both based on QCM6490. Signed-off-by: Jiali Chen <chenjiali@radxa.com>
The clk-pwm driver uses the default of_pwm_xlate_with_flags() translation, which supports index, period and flags in a three-cell specifier. Allow that standard form while retaining the existing two-cell binding. Signed-off-by: Jiali Chen <chenjiali@radxa.com>
Add the fixed 3.3 V enable rail used to keep the onboard Wi-Fi module powered. Also constrain PM8350C LDO5 to the 3.296 V level used by the board. Signed-off-by: Jiali Chen <chenjiali@radxa.com>
Add the board description for the QCM6490-based Radxa Dragon Q6B, including its power, storage, USB, display, audio, cooling, PCIe and Ethernet topology. Add the matching KVM overlay for the PCIe address space, remote processor reset handling and video IOMMU assignments used with Hypervisor Override. Signed-off-by: Jiali Chen <chenjiali@radxa.com>
The Dragon Q6B firmware exposes validated QSEECOM and SCM storage interfaces. Add the exact machine compatible to both allowlists without widening access to other QCM6490 systems. Signed-off-by: Jiali Chen <chenjiali@radxa.com>
Limit Dragon Q6B to the validated high-bandwidth mode range. Apply board mode filters before the DSC early return so compressed modes cannot bypass the platform restriction. Signed-off-by: Jiali Chen <chenjiali@radxa.com>
…isplay_8hd_ad002" This reverts commit 23269b2.
| pinctrl-0 = <&wifi_pwr_en>; | ||
| pinctrl-names = "default"; | ||
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| regulator-boot-on; |
| @@ -489,9 +505,9 @@ | |||
| }; | |||
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| vreg_l5c_1p62: ldo5 { | |||
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这个是不是跟其他的kvm overlay一样的？在makefile里面可以怎么复用一下么
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| &remoteproc_cdsp { | ||
| firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn"; |
| cpuss0-thermal { | ||
| polling-delay-passive = <100>; | ||
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| trips { |
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| trips { | ||
| cpuss0_fan_trip: fan { | ||
| temperature = <65000>; |
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