IMX708 ccs and link frequency changes - #7605
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When the PLL is configured in DUAL_MODE (separate VT and OP trees) and the sensor's FIFOs allow derating and/or overrating, the VT pixel rate might be higher or lower than OP pixel rate. Support such usecases by allowing an optional input for the target VT pixel rate. Signed-off-by: Jai Luthra <jai.luthra@ideasonboard.com>
Replace the PLL dividers and multipliers hard coded into the mode and link frequency register lists with a call to the CCS PLL calculator. The pre-PLL dividers match values those currently in use, and the CCS PLL calculator generates the same register values as what's in the current mode list. Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
Give each mode an array of timings rather than one fixed set, so that a mode can run faster when the link has the bandwidth for it. The entry a mode lists first is its default, used for any link frequency it has no timing for, which leaves every existing mode behaving as before. Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
Add timings for a 960MHz link frequency, which gives the full resolution mode enough bandwidth to reach 30fps in 2-lane mode, and roughly doubles the rate of the binned modes. Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
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