ComputerArchi

Verilog modules covering the single cycle processor

Name		Name	Last commit message	Last commit date
Latest commit History 17 Commits
Lab1-Multiplexer		Lab1-Multiplexer
Lab2-ALUControl		Lab2-ALUControl
Lab3-Register		Lab3-Register
Lab4-Memory		Lab4-Memory
Lab5-ControlUnit		Lab5-ControlUnit
Lab6-EverythingSoFar		Lab6-EverythingSoFar
Lab7-Branch		Lab7-Branch
CECS 341 - Lab 3A.PNG		CECS 341 - Lab 3A.PNG
CECS 341 - Lab 3B.PNG		CECS 341 - Lab 3B.PNG
CECS 341 - Lab 3C.PNG		CECS 341 - Lab 3C.PNG
Lab 4a Output.PNG		Lab 4a Output.PNG
README.md		README.md

Provide feedback