Education kit for teaching VLSI fundamentals through practical microprocessor design using industry EDA tools (educational)

5 Day TCL begginer to advanced training workshop by VSD

This repository contains all major projects completed as part of the EECS 4612: Digital VLSI Design course at York University. The projects showcase the complete ASIC design flow — from RTL design to GDSII layout — using industry-grade tools like Cadence Genus, Innovus, and Virtuoso.

Proteus Design Suite Professional — electronics simulation with SPICE, PCB layout and microcontroller co-simulation.

A web-based tool for parsing and visualizing FPGA. It provides an interactive graph representation of signal propagation, helping engineers and students analyze delays, interconnections, and logic components inside an FPGA.

Param + EDA — a hierarchical configuration system for EDA tooling: config-folder tree with parent/child scoping, lazy variable substitution, and JSON-backed load/save.

A collection of Schematics, PCBs and VLSI work on various platforms

AI-powered Verilog/SystemVerilog MCP Server for Claude Code: generate testbenches, lint RTL code, and scaffold UVM verification environments

Browser cockpit & IDE for the LibreLane RTL-to-GDS chip flow — run, verify, and explore silicon flows without living in a terminal.

Static timing analysis with signal integrity — WNS/TNS sign-off gate, SI/crosstalk + statistical OCV.

Design and simulation of 16-bit Ripple Carry and Weinberger Adders using Cadence Virtuoso. Includes full adder modeling, schematic creation, waveform analysis, and detailed delay-power comparison.

An integrated educational framework covering semiconductor physics, circuit design, fabrication processes, and testing — from fundamentals to advanced practical applications. （物性・回路・プロセス・設計・テストを貫く一貫教育体系。基礎から応用・実践までを体系的に整理）

OS-independent CLI tool that checks dependencies for eSim's integrated EDA tools (Ngspice, KiCad, Scilab, Verilator) across Windows, Linux, and macOS. Built as a screening task for the FOSSEE Semester Long Internship.

Layout-vs-schematic: SPICE netlist comparison with clear divergence diagnostics.

A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.

Use GPT-4 to generate, simulate, and visualize Verilog modules from natural language prompts.

RC parasitic extraction — routed layout to SPEF; a calibrated sky130 deck tracks OpenRCX.

Liberty characterization — SPICE + PDK models to .lib (NLDM + CCS), parallel-SPICE orchestration.

Static glitch/hazard analysis: a gate-level netlist + Liberty in, reconvergent-fanout hazards out.

Personal GitHub repository for experiments, project tests, and general development work.