FROMLIST: phy: qcom-qmp-ufs: Add Glymur support - #1833
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September 15, 2026 11:01
…r QMP UFS PHY Document the QMP UFS PHY on Glymur SoC. Link: https://lore.kernel.org/all/20260911-glymur_ufs_qcb_enablement-v1-1-b9fc5e2ee99a@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Document UFS Host Controller on Glymur SoC. Glymur UFSHC has a multi-queue command (MCQ) register range in addition to the standard one. So, both reg entries are required. Link: https://lore.kernel.org/all/20260911-glymur_ufs_qcb_enablement-v1-2-b9fc5e2ee99a@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
Add the init sequence tables and config for the UFS QMP phy found in the Glymur SoC. Link: https://lore.kernel.org/all/20260911-glymur_ufs_qcb_enablement-v1-5-b9fc5e2ee99a@oss.qualcomm.com/ Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
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Add the init sequence tables and config for the UFS QMP phy found in the Glymur SoC.
Link: https://lore.kernel.org/all/20260911-glymur_ufs_qcb_enablement-v1-5-b9fc5e2ee99a@oss.qualcomm.com/