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nitinrawat123 merged 3 commits into from
Sep 25, 2026
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FROMLIST: phy: qcom-qmp-ufs: Add Glymur support #1833

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68f03de
FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Document Glymu…
Pradeep-pvk Sep 11, 2026
c5bd20d
FROMLIST: scsi: ufs: qcom: dt-bindings: Document Glymur UFS controller
Pradeep-pvk Sep 11, 2026
ee27f92
FROMLIST: phy: qcom-qmp-ufs: Add Glymur support
Pradeep-pvk Sep 11, 2026
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2 changes: 2 additions & 0 deletions Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@ properties:
- qcom,kaanapali-qmp-ufs-phy
- const: qcom,sm8750-qmp-ufs-phy
- enum:
- qcom,glymur-qmp-ufs-phy
- qcom,milos-qmp-ufs-phy
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
Expand Down Expand Up @@ -108,6 +109,7 @@ allOf:
compatible:
contains:
enum:
- qcom,glymur-qmp-ufs-phy
- qcom,milos-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
Expand Down
3 changes: 3 additions & 0 deletions Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml
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Expand Up @@ -16,6 +16,7 @@ select:
contains:
enum:
- qcom,eliza-ufshc
- qcom,glymur-ufshc
- qcom,hawi-ufshc
- qcom,kaanapali-ufshc
- qcom,nord-ufshc
Expand All @@ -29,6 +30,7 @@ properties:
items:
- enum:
- qcom,eliza-ufshc
- qcom,glymur-ufshc
- qcom,hawi-ufshc
- qcom,kaanapali-ufshc
- qcom,nord-ufshc
Expand Down Expand Up @@ -78,6 +80,7 @@ allOf:
contains:
enum:
- qcom,eliza-ufshc
- qcom,glymur-ufshc
- qcom,nord-ufshc
then:
properties:
Expand Down
99 changes: 99 additions & 0 deletions drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
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Expand Up @@ -84,6 +84,59 @@ static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL,
};

static const struct qmp_phy_init_tbl glymur_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0xce),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x24),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x24),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0xe0),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30),
QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77),
};

static const struct qmp_phy_init_tbl milos_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
Expand Down Expand Up @@ -1227,6 +1280,11 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
}

/* Regulator bulk data with load values for specific configurations */
static const struct regulator_bulk_data glymur_ufsphy_vreg_l[] = {
{ .supply = "vdda-phy", .init_load_uA = 217130 },
{ .supply = "vdda-pll", .init_load_uA = 18340 },
};

static const struct regulator_bulk_data milos_ufsphy_vreg_l[] = {
{ .supply = "vdda-phy", .init_load_uA = 140120 },
{ .supply = "vdda-pll", .init_load_uA = 18340 },
Expand Down Expand Up @@ -1325,6 +1383,44 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = {
.rx2 = 0x1a00,
};

static const struct qmp_phy_cfg glymur_ufsphy_cfg = {
.lanes = 2,

.offsets = &qmp_ufs_offsets_v6,
.max_supported_gear = UFS_HS_G5,

.tbls = {
.serdes = sm8750_ufsphy_serdes,
.serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes),
.tx = sm8750_ufsphy_tx,
.tx_num = ARRAY_SIZE(sm8750_ufsphy_tx),
.rx = glymur_ufsphy_rx,
.rx_num = ARRAY_SIZE(glymur_ufsphy_rx),
.pcs = sm8750_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs),
},

.tbls_hs_b = {
.pcs = sm8750_ufsphy_hs_b_pcs,
.pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs),
},

.tbls_hs_overlay[0] = {
.pcs = sm8750_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs),
.max_gear = UFS_HS_G4,
},
.tbls_hs_overlay[1] = {
.pcs = sm8650_ufsphy_g5_pcs,
.pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs),
.max_gear = UFS_HS_G5,
},

.vreg_list = glymur_ufsphy_vreg_l,
.num_vregs = ARRAY_SIZE(glymur_ufsphy_vreg_l),
.regs = ufsphy_v6_regs_layout,
};

static const struct qmp_phy_cfg milos_ufsphy_cfg = {
.lanes = 2,

Expand Down Expand Up @@ -2259,6 +2355,9 @@ static int qmp_ufs_probe(struct platform_device *pdev)

static const struct of_device_id qmp_ufs_of_match_table[] = {
{
.compatible = "qcom,glymur-qmp-ufs-phy",
.data = &glymur_ufsphy_cfg,
}, {
.compatible = "qcom,milos-qmp-ufs-phy",
.data = &milos_ufsphy_cfg,
}, {
Expand Down
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