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Route all 47 AM3352 signals with the public bus_lanes phase - #4237

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seveibar merged 6 commits into
docs/bus-lanes-integrated-dogbonesfrom
feat/integrated-bus-lanes
Sep 30, 2026
Merged

seveibar merged 6 commits into
docs/bus-lanes-integrated-dogbonesfrom
feat/integrated-bus-lanes

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@seveibar seveibar commented Sep 30, 2026 •

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The original AM3352/RAM board now routes all 47 signals with zero native DRC errors through the public phase:

<autoroutingphase name="DDR_BUS_LANES" phaseIndex={1} autorouter="bus_lanes" />

The fixture preserves the reference TSX's footprints, placement, 47 connections, two byte buses, three differential pairs, and timing constraints. It contains no custom algorithm or saved route plan. Automatic dogbones apply only to untouched component pads; existing fanout handoffs stay fixed.

Completed AM3352 signal layers

Start review with tests/features/autorouter-bus-lanes-am3352.test.tsx and its three signal-layer SVG snapshots. Every snapshot is written only after these gates pass:

  • 47 distinct routes, zero native circuit errors, exactly two local vias per signal, and a single-layer via-free carrier.
  • 1549.71 mm total copper (limit 1700); maximum/mean detour 2.047/1.546 (limits 2.6/1.75).
  • 540 ordinary turns and 145 short jogs (limits 900/460), with zero acute corners.
  • Byte skew ≤0.635 mm; pair skew ≤0.127 mm, including fixed dogbones.
  • Pair interior edge gaps 0.11213–0.13813 mm, inside the unchanged 0.0999–0.155 mm limits and 6.2 mm per-end approach allowance.

The source-bus assertion includes both byte buses and all three exported differential-pair memberships. The snapshot views explicitly select inner1, inner2, and bottom so the carrier routing is visible. No partial/unrouted AM3352 artifacts are included.

Validation: fresh TSX integration run passed in 281 seconds with 169 assertions; six smaller bus_lanes integration tests and core typecheck pass. The test timeout is 900 seconds for this dense regression. The solver has 49 passing tests and four passing DDR benchmarks; see solver #3.

Dependencies: props uses the built, commit-pinned PR preview from props #875 in both devDependencies and overrides. Replace this preview with its npm release before merge. The dist build and smoke test pass from a clean CI install. The dense AM3352 test has a dedicated Ubuntu ARM job matching the snapshot-update runner, with all 169 assertions and zero image-diff tolerance. Other tests continue in the ten x86 shards. ARM and x86 can select different valid control paths due to floating-point geometry differences. The tested solver is pinned to de425372f6413e024010d24b64341d64c83a6a12, which uses fanout-solver #252. This PR is stacked on planning #4232.

CI is green on fa67b539ed24f804820a4e8af5172d5b81a9bf92: all ten x86 test shards, the dedicated AM3352 ARM routing/snapshot job (169 assertions), dist build/smoke test, and Vercel preview pass. Test run. No routing assertions, DRC gates, image tolerances, or snapshot geometry were weakened or changed.

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@seveibar seveibar changed the title Integrate bus_lanes dogbones and add AM3352 TSX regression Verify public bus_lanes phase against AM3352 routing quality Sep 30, 2026
@seveibar seveibar changed the title Verify public bus_lanes phase against AM3352 routing quality Route all 47 AM3352 signals with the public bus_lanes phase Sep 30, 2026
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seveibar marked this pull request as ready for review September 30, 2026 21:43
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seveibar merged commit 998f772 into docs/bus-lanes-integrated-dogbones Sep 30, 2026
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seveibar deleted the feat/integrated-bus-lanes branch September 30, 2026 21:43

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Preview — fa67b539 Deployed Sep 30, 2026 by vercel[bot]
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