V80 300mhz - #410
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Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> (cherry picked from commit 639c8c8)
All three are implementation-only; the logic is unchanged. VX_cp_dma next_chunk: min(MAX_BURST - s, MAX_BURST - d) is rewritten as MAX_BURST - max(s, d). cl_idx is 6 bits so beats_to_4k never underflows and the identity holds. One 6-bit compare then a subtract, instead of two subtracts then a compare, off the src_r -> chunk_beats path. VX_cp_dma read-ready: the decode drives the clock enable of all 264 bits of the feeding stream buffer, which the placer spreads far from the FSM -- three logic levels of 0.267ns behind 2.008ns of route. MAX_FANOUT=32 lets each replica enable a nearby group. VX_cp_fetch ring_base: the value lives in the AXI-Lite regfile, placed far from the engine, and fed the address adder directly. It is quasi-static (the host writes it during queue setup and it cannot change while a fetch is in flight), so a locally registered copy is equivalent and keeps that route out of the adder. Measured +0.332 ns together. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> (cherry picked from commit 4c4f79d)
VX_POST_PHYSOPT (off by default) enables post-route physical optimization.
After the static shell was rebuilt with its vNOC memory ingress pinned to
SLR2, a tinyGPU RM closed at WNS -0.034 with 265 endpoints averaging -13 ps,
the worst being a replica-to-replica hop on offset_r -- fanout-driven, not
logic depth. phys_opt recovers exactly that, taking the build to 300.000 MHz.
It deliberately does not touch the placer strategy. That experiment is still
validly disproven and the warning block above it stays in force.
The rest is the negative record, kept because it is expensive to rediscover.
pre_synth_hook and the two hw/scripts hooks carry the measurements inline:
free placement WNS -0.260 942 failing
confine AFU to SLR1 WNS -0.801
confine AFU to SLR2 WNS -1.599
clear BalancedSLR strategy WNS -0.343 4831 failing
confine SmartConnects to SLR2 WNS -0.326 3216 failing
steer vNOC NMUs to SLR2 DRC HDPR-122 -- impossible from the RM
Both hw/scripts are gated off by default and are sourced by pre_opt_hook, so
they have to be present for the flow to run. xilinx_noc_slr_steer.tcl records
why the RM cannot move a locked NoC port: each has exactly one allowed site,
fixed by the prebuilt shell. That is what motivated the shell-side fix.
The matching build_*.sh are the recipes for each measurement above.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
(cherry picked from commit ce97044)
VORTEX_AVED_NO_PROGRAM is gone. It defaulted hardware runs to "do not program the PL" because, on a board whose static shell was never written to OSPI flash, vrtd's requested-vs-current shell comparison never settles, so a design write could fail mid-flight and take the AMC to NO_AMC. That is a property of an unflashed board, not of the driver. With the shell in flash the driver now programs on open exactly as the XRT driver's load_xclbin() does, and the switch, its plumbing in tests/regression/common.mk, and the /tmp/v80_resident_afu.path fallback that existed to run against whatever happened to be resident are all removed. Validated on silicon: sgemm PASSED against the default config with no environment overrides beyond FPGA_BIN_DIR. The four tools under hw/syn/xilinx/aved/tools that set it are updated; the JTAG-load-then-never-reprogram flow they implement is no longer required. Post-route phys_opt is now unconditional rather than gated on VX_POST_PHYSOPT. It is not an experiment -- it is what closes 300 MHz (-0.034 -> 0.000). Deletes xilinx_dfx_slr_confine.tcl and xilinx_noc_slr_steer.tcl and their sourcing. Both were disproven: pblock confinement measured worse than free placement in every variant, and steering NoC ports from an RM is refused by DRC HDPR-122 in principle. Their measurements are kept as comments in pre_synth_hook.tcl, which is the useful part; the dead code is not. Also deletes the per-experiment build_*.sh wrappers. The canonical invocation is `make all TARGET=hw [CONFIGS=...]`. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> (cherry picked from commit 2ecdb3d)
xilinx_slash_setup.md documented flashing as `ami_tool cfgmem_program -p 0` followed by a reboot. That writes one partition and is not the path that works. Replaced with the verified `v80-smi write-static-shell --flash` sequence, including the four traps: --pdi is effectively mandatory (without it v80-smi can resolve the root-owned dist-packages copy and silently reflash an older shell), both boot partitions must be written because POST reads partition 0 and a compute-only write passes every test until the next reboot and then loses the card, --flash needs the FPT image rather than _nofpt, and --shell-type all is rejected alongside --pdi. Also records that no reboot or power cycle is needed: each write resets the link and rescans, and the board returns on its own. aved_driver_architecture.md still described VORTEX_AVED_NO_PROGRAM as current. It was removed; the driver always programs, as XRT's load_xclbin() does. The section now explains that the hazard it guarded was a property of an unflashed board -- vrtd's requested-vs-current shell comparison never settling -- and that writing the shell to flash is the actual fix, along with why the resident-vbin fallback went too: it silently attributes results to the wrong bitstream when FPGA_BIN_DIR changes. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com> (cherry picked from commit 03b16265e7c01fbc3b56df39ce647232aaa8e989)
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