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ASIC Gate ASIC Gate #6: Scheduled
3m 36s master
master
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Queued master
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CI CI #1803: Scheduled
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ASIC Gate ASIC Gate #5: Scheduled
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ASIC Gate ASIC Gate #4: Scheduled
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FPGA Gate FPGA Gate #8: Scheduled
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ASIC Gate ASIC Gate #3: Scheduled
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FPGA Gate FPGA Gate #7: Scheduled
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Fix barrier phase routing and global response tracking CI #1802: Pull request #407 synchronize by tinebp
17h 41m 8s fix/gbar-response-phase
fix/gbar-response-phase
17h 41m 8s
Merge branch 'master' into fix/gbar-response-phase CI #1801: Commit 536489b pushed by tinebp
16h 30m 40s fix/gbar-response-phase
fix/gbar-response-phase
16h 30m 40s
tests/regression: gbar_phase — expose the global barrier's lost phase… CI #1800: Commit bba80f8 pushed by tinebp
14h 10m 28s master
master
14h 10m 28s
Bug/gbar response phase CI #1799: Pull request #403 synchronize by tinebp
8h 53m 58s RunjiaChen:bug/gbar-response-phase
RunjiaChen:bug/gbar-response-phase
8h 53m 58s
tests/regression: bar_slot_phase — expose cross-slot barrier phase co… CI #1798: Commit 9ab699e pushed by tinebp
15h 37m 26s master
master
15h 37m 26s
tests/regression: bar_slot_phase — expose cross-slot barrier phase co… CI #1797: Pull request #402 synchronize by tinebp
8h 55m 51s RunjiaChen:bug/bar-slot-phase-v2
RunjiaChen:bug/bar-slot-phase-v2
8h 55m 51s
fix the bug of global barrier and add the tests that can reproduce the previous bug. CI #1796: Pull request #412 opened by symmetryyyyy
5h 1m 57s review/gbar-response-phase-20260903
review/gbar-response-phase-20260903
5h 1m 57s
tests: finalize global barrier regression matrix CI #1795: Commit bc90d02 pushed by symmetryyyyy
4h 30m 31s review/gbar-response-phase-20260903
review/gbar-response-phase-20260903
4h 30m 31s
ASIC Gate ASIC Gate #2: Scheduled
3m 52s master
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FPGA Gate FPGA Gate #6: Scheduled
1d 1h 12m 45s master
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fix(gbar): retire responses by barrier id CI #1794: Commit 9e5f577 pushed by symmetryyyyy
4h 25m 2s review/gbar-response-phase-20260903
review/gbar-response-phase-20260903
4h 25m 2s
simx: reject RV32 shift-immediate code points with shamt[5] set CI #1793: Pull request #411 opened by Lfan-ke
Action required Lfan-ke:fix/rvc-shamt5-rv32
Lfan-ke:fix/rvc-shamt5-rv32
Action required
ASIC Gate ASIC Gate #1: Scheduled
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FPGA Gate FPGA Gate #5: Scheduled
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V80 300mhz (#410) CI #1792: Commit 5def825 pushed by tinebp
10h 43m 23s master
master
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V80 300mhz CI #1791: Pull request #410 synchronize by tinebp
3m 15s v80-300mhz
v80-300mhz
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